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Tracking
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Thu, 13 Aug 2026 11:00:00 +0000
| Type | Values Removed | Values Added |
|---|---|---|
| First Time appeared |
Intel
Intel xeon |
|
| Vendors & Products |
Intel
Intel xeon |
Wed, 12 Aug 2026 15:30:00 +0000
| Type | Values Removed | Values Added |
|---|---|---|
| Metrics |
ssvc
|
Tue, 11 Aug 2026 17:00:00 +0000
| Type | Values Removed | Values Added |
|---|---|---|
| Description | Improper handling of overlap between protected memory ranges for some Intel(R) Xeon(R) 6 processors when using Intel(R) TDX within SMM may allow an escalation of privilege. SMM adversary with a privileged user combined with a high complexity attack may enable escalation of privilege. This result may potentially occur via local access when attack requirements are present with special internal knowledge and requires no user interaction. The potential vulnerability may impact the confidentiality (high), integrity (high) and availability (none) of the vulnerable system, resulting in subsequent system confidentiality (none), integrity (none) and availability (none) impacts. | |
| Weaknesses | CWE-1260 | |
| References |
| |
| Metrics |
cvssV4_0
|
Status: PUBLISHED
Assigner: intel
Published:
Updated: 2026-08-12T14:46:56.476Z
Reserved: 2025-04-10T03:00:30.747Z
Link: CVE-2025-31936
Updated: 2026-08-12T13:33:37.744Z
Status : Awaiting Analysis
Published: 2026-08-11T17:17:43.500
Modified: 2026-08-12T20:54:11.500
Link: CVE-2025-31936
No data.
OpenCVE Enrichment
Updated: 2026-08-13T10:40:12Z